📄️ Key Concepts
Floorplanning In-Depth
📄️ Floorplanning in OpenLANE
Create the Floorplan
📄️ Binding and Placement
Logical gates in the netlist are abstract. For example, an AND gate in your schematic is just a symbol. But to actually make it on a chip, you need to pick a real, physical implementation of that gate — with transistors laid out, wiring, dimensions, etc. This is done by binding the netlist to a standard cell library.
📄️ Cell Design
Inputs for Standard Cell Design Flow
📄️ Timing
Timing Threshold Definitions